1. Field of the Invention
The present invention relates to a semiconductor device in which a plurality of impurity layers are formed in a semiconductor substrate by ion implantation, and to a manufacturing method thereof.
2. Description of the Background Art
A main surface of a semiconductor substrate is classified into element forming regions and element isolating regions. In an element forming region, an element such a-MOS transistor is formed. An element isolating region has an isolating insulating film formed to surround the element forming region for electrically isolating adjacent element forming regions from each other.
FIG. 15 is an illustration of an MOS type semiconductor device viewed from above, and FIGS. 16 and 17 are cross sections taken along the lines E--E' and F--F' of FIG. 15, respectively.
As shown in the figure, the main surface of a semiconductor substrate 1 formed of single crystal of silicon, for example, includes an element forming region 2 and an element isolating region 3 surrounding element forming region 2. In element isolating region 3, an isolating insulating film 4 for electrically isolating adjacent element forming regions 2 from each other is formed. Isolating insulating film 4 is an oxide film formed, for example, by thermal oxidation.
A gate electrode layer 5 formed of polycrystalline silicon, for example, extends over element forming region 2 and element isolating region 3. As shown in FIG. 15, element forming region 2 has a source region 6 and a drain region 7 of the MOS transistor on one side and on the other side of gate electrode layer 5, respectively.
As shown in FIGS. 16 and 17, a first impurity layer 8 is formed near the main surface of element forming region 2, a second impurity layer 9 is formed at a position deeper than that, and a third impurity layer 10 is formed at a position still deeper than that. The second and third impurity layers 9 and 10 are formed entirely in a direction parallel to the surface of semiconductor substrate 1. The first, second and third impurity layers 8, 9 and 10 are formed by the same conductivity type impurity as that of substrate 1.
When a p channel MOS transistor is to be formed, source region 6 and drain region 7 are formed by implanting, for example, boron to the main surface of element forming region 2. When an n channel MOS transistor is to be formed, source region 6 and drain region 7 are formed by implanting phosphorus or arsenic to the main surface of element forming region 2.
FIG. 18 shows a distribution curve of impurity concentration viewed along the line G--G' of FIG. 16, while FIG. 19 shows a distribution curve of impurity concentration viewed along the line X--X' of FIG. 16.
First impurity layer 8 is formed for adjusting threshold voltage of the transistor, and peak impurity concentration thereof is positioned at a depth of at most 0.2 .mu.m from the main surface of element forming region 2.
The function of second impurity layer 9 positioned below isolating insulating film 4 differs from the function of the same positioned below element forming region 2. Namely, that region of the second impurity layer 9 which is positioned below isolating insulating film 4 is to enhance ability of element isolation. More specifically, it serves to increase threshold voltage of a parasitic field transistor to suppress punch through between elements. The function of that region of the second impurity layer 9 which is positioned below element forming region 2 is to adjust substrate constant and junction capacitance. More specifically, it serves to eliminate lower concentration portion of the well to suppress punch through of the transistor.
The peak impurity concentration of that region of second impurity layer 9 which is positioned below isolating insulating film 4 is within the depth range of at most 0.1 .mu.m from the lower surface of the isolating insulating film, while the peak impurity concentration of that region of second impurity layer 9 which is positioned below element forming region is within a depth range of from 0.4 .mu.m to 0.5 .mu.m from the main surface of the substrate.
The function of the third impurity layer 10 is to lower well resistance. More specifically, when CMOS circuit is formed at the element forming region 2, it increases latch up resistance. When a memory cell is formed in the element forming region, it increases soft error resistance. Further, it suppresses diffusion component of leak current. Below isolating insulating film.4, the third impurity layer 10 has peak impurity concentration within the depth range from 0.7 .mu.m to 1.0 .mu.m from the lower surface of the isolating insulating film, and below element forming region 2, it has peak impurity concentration within depth range from 1.1 .mu.m to 1.4 .mu.m from the main surface of the substrate.
Among impurity concentrations of the first, second and third impurity layers 8, 9 and 10, the peak value of second impurity layer 9 is the smallest.
Conventionally, the first, second and third impurity layers 8, 9 and 10 have been formed in the following manner. First, by ion implantation of impurity to the entire main surface of semiconductor substrate 1 on which isolating insulating film 4 has been formed, second and third impurity layers 9 and 10 are formed. The depth of the impurity layer formed by ion implantation through the main surface of element forming region 2 comes to be different from the depth of the impurity layer formed by ion implantation through the thick isolating insulating film 4. As shown in FIGS. 16 and 17, the second and third impurity layers 9 and 10 are formed to be deep below element forming region 2 and shallow below isolating insulating film 4. After the formation of the second and third impurity layers 9 and 10, by ion implantation of impurity to the entire main surface of semiconductor substrate 1, first impurity layer 8 is formed near the main surface of semiconductor substrate 1. At this time, since the energy of ion implantation for forming the first impurity layer is small, an impurity layer is not formed in the element isolating region.
The conventional semiconductor device such as described above suffers from the following problems. Second impurity layer 9 has different functions at a region positioned below element forming region 2 and at a region positioned below element isolating region 3. The region of the second impurity layer 9 positioned below isolating insulating film 4 has a function of increasing ability to isolate elements, while the region below element forming region 2 has a function of adjusting substrate constant and junction capacitance.
As the degree of integration of the semiconductor device has been increased, higher ability of isolation has been required of the element isolating region. In order to improve the ability of isolating elements, it is necessary to increase impurity concentration of the second impurity layer 9 positioned below isolating insulating film 4. The peak value of impurity concentration of second impurity layer 9 in the region below element forming region 2 is not different from that in the region below element isolating region 3. Therefore, in order to improve ability of isolation, it is necessary to increase impurity concentration of the whole region of second impurity layer 9. When the second impurity layer 9 positioned below element forming region 2 comes to have higher impurity concentration, it means that impurity concentration of the element forming region as a whole is increased. This results in larger substrate constant, and larger fluctuation of the threshold voltage when a bias voltage is applied to the substrate. When the threshold voltage becomes higher, drain current becomes smaller and the difference between operational voltage applied to the gate and threshold voltage becomes smaller, which affects speed of response of the circuit.
Further, junction capacitance formed between the substrate and impurity layers of high concentration forming source and drain regions 6 and 7 increases as the impurity concentration of the substrate becomes higher. Therefore, if the-impurity concentration of second impurity layer 9 is increased, the junction capacitance increases as well, affecting the speed of response of the circuit.
In order to suppress increase of substrate constant and of the junction capacitance, the impurity concentration of second impurity layer 9 positioned below element forming region 2 should be decreased, and the peak impurity concentration should be positioned deeper. However, if these conditions are satisfied, the ability of isolating elements of second impurity layer 9 positioned below isolating insulating film 4 would be degraded.
In the conventional semiconductor device, if the ability of isolation between elements is to be improved, operational characteristics of the elements such as transistors are degraded, while if the operational characteristics of the elements are to be improved, ability of isolation between elements is degraded.